Introduction

The goal of this workshop is to bring researchers and practitioners of VLSI testing from all over the world together to exchange ideas and experiences in register transfer level (RTL) and high level testing. WRTLT'17, the 18th workshop, will be held in conjunction with the 26th Asian Test Symposium (ATS'17) in Taipei, Taiwan. We hope and expect this workshop provides an ideal forum for deep discussion on this important topic for the future system-on-a-chip (SoC) designs and 3D integrated circuits.

Call for paper

Submission Topics

Areas of interest include but are not limited to:

  • RTL fault modeling, RTL ATPG, RTL DFT, RTL BIST

  • High-level/behavior fault modeling, testing and synthesis for testability

  • Functional fault modeling and test bench generation

  • 3D IC testing

  • SoC/NoC testing, test scheduling, core-based testing, interconnect testing

  • Dependable SoC: design for dependability, self-repair techniques, fault-tolerant SoCs

  • Microprocessor testing and design verification

  • Low power testing and Test compression

  • Hardware trojan detection and secure testing

Submit Comment
Verify Code Change Another
All Comments
Important Date

  • Conference Date

    Nov 30

    2017

    to

    Dec 01

    2017

  • Dec 01 2017

    Registration deadline

Sponsored By
IEEE Computer Society
Contact Information
Login to view full contact details
Previous Conferences