2017 IEEE 35th International Conference on Computer Design (ICCD)

Authors are asked to submit technical papers in accordance to the author’s instructions in one of the following five conference tracks:

• Computer Systems and Applications:

Advanced computer architecture for general and application-specific enhancement; Software design for embedded, mobile, general-purpose, cloud, and high-performance platforms; IP and platform-based designs; HW/SW codesign; Modeling and performance analysis; Support for security, languages and operating systems; Hardware/software techniques for embedded systems; Application-specific and embedded software optimization; Compiler support for multi-threaded and multi-core designs; Memory system and network system optimization; On-chip and system-area networks; Support for communication and synchronization.

• Processor Architecture: 

Microarchitecture design techniques for uni- and multi-core processors: instruction-level parallelism, pipelining, caching, branch prediction, multithreading; Techniques for low-power, secure, and reliable processors; Embedded, network, graphic, system-on-chip, applicationspecific and digital signal processor design; Hardware support for processor virtualization; Real-life design challenges: case studies, tradeoffs, postmortems.

• Logic and Circuit Design: 

Circuits and design techniques for digital, memory, analog and mixed-signal systems; Circuits and design techniques for high performance and low power; Circuits and design techniques for robustness under process variability and radiation; Design techniques for emerging process technologies (MEMs, spintronics nano, quantum, flexible electronics); Asynchronous circuits; Signal processing, graphic processor and arithmetic circuits.

• Electronic Design Automation: 

High-level, logic and physical synthesis; Physical planning, design and early estimation for large circuits; Automatic analysis and optimization of timing, power and noise; Tools for multiple-clock domains, asynchronous and mixed timing methodologies; CAD support for FPGAs, ASSPs, structured ASICs, platform-based design and NOC; DfM and OPC meth-odologies; System-level design and synthesis; Tools and design methods for emerging technologies (MEMs, spintronics, nano, quantum).

• Test, Verification and Security:

 Design error debug and diagnosis; Fault modeling; Fault simulation and ATPG; Analog/RF Testing; Statistical Test Methods; Large volume yield Analysis and Learning; Fault tolerance; DFT and BIST; Functional, transaction-level, RTL, and gate-level modeling and verification of hardware designs; Equivalence checking, property checking, and theorem proving; Constrained-random test generation; High-level design and SoC validation. Hardware security primitives; Side channel analysis; Logic and microarchitectural countermeasures; Hardware security for IoT; Interaction between VLSI test and trust.