Introduction

ReConFig 2017 will provide a leading edge forum for researchers and engineers from across the world to present their latest research and to discuss future research and applications. The conference seeks to promote the use of reconfigurable computing and FPGA technology for research, education, and applications, covering from hardware architectures and devices to custom computers and high performance systems. 

Call for paper

Important date

2017-07-21
Abstract submission deadline
2017-07-21
Draft paper submission deadline
2017-09-22
Draft paper acceptance notification
2017-10-13
Final paper submission deadline

Submission Topics

ReConFig covers a broad spectrum of topics including, but not limited to:

  • Models, methods, tools, and architectures for reconfigurable computing

  • Compilation, simulation, debugging, synthesis, verification, and test of reconfigurable systems

  • Field programmable gate arrays and other reconfigurable technologies

  • Evolvable hardware and dynamic reconfiguration

  • Algorithms implemented on reconfigurable hardware

  • Reconfigurable computing education

  • Reconfigurable computing applications

In addition to the general session, submissions are invited for the following tracks:

  • Reconfigurable Computing for Networks and Communications

  • Reconfigurable Computing with GPUs and APUs

  • High Performance Reconfigurable Computing

  • Multiprocessor Systems and Networks on Chip

  • Productivity Environments and High Level Languages

  • Reconfigurable Computing for Signal Processing

  • Reconfigurable Computing for Security and Cryptography

  • Reconfiguration Techniques

  • Reconfigurable Computing in Space

  • Phd Forum

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Important Date
  • Conference Date

    Dec 04

    2017

    to

    Dec 06

    2017

  • Jul 21 2017

    Abstract Submission Deadline

  • Jul 21 2017

    Draft paper submission deadline

  • Sep 22 2017

    Draft Paper Acceptance Notification

  • Oct 13 2017

    Final Paper Deadline

  • Dec 06 2017

    Registration deadline

Sponsored By
Instituto Nacional de Astrofisica, Optica y Electronica - Mexico
Supported By
IEEE Circuits and Systems Society
IEEE Puebla Section CAS Chapter
Contact Information