Introduction
The growing complexity and shrinking geometries of modern manufacturing technologies are making devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, both in safety-critical aerospace and automotive applications and also for large scale servers and high performance applications.
The SELSE workshop provides a unique forum for discussion of current research and practice in system-level error management. SELSE solicits papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also welcome.
We are happy to announce that the best papers presented at SELSE will be selected for inclusion in the “Best of SELSE” session at IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2021. These papers will be selected based on the importance of the topic, technical contributions, quality of results, and authors’ agreement to travel to present at DSN in Taipei, Taiwan on June 21 – June 24, 2021.
Sponsor Type:1
Committee
General Co-Chairs
Paolo Rech, UFRGS
Stefano Di Carlo, Politecnico di Torino
Laura Monroe, LANL (Emerita)
John Daly, LPS (Emeritus)
Program Co-Chairs
Qiang Guan, Kent State
Carles Hernández, UPV
Finance Chair
Marcelo Brandalero, Brandenburg University of Technology Cottbus-Senftenberg
Registration Chair
Karthik Swaminathan, IBM
Local Arrangements Chair
Irina Alam, UCLA
Publicity Co-Chairs
Michael Sullivan, NVIDIA (North America)
Tiago Balen, UFRGS (South America)
Stefano Di Carlo, PoliTo (Europe)
Yi-Pin Fang, TSMC (Asia)
Bay Area Industry Liaisons
Shahrzad Mirkhani, Bigstream
Mark Gottscho, Google
Webmaster
Vanessa Job, LANL/UNM
Daniel Oliveira, UFPR
Advisors to the Committee
Sarah Michalak, LANL
Alan Wood, Oracle
Vilas Sridharan, AMD
Call for paper
Important date
Submission Topics
Key areas of interest include (but are not limited to):
Error rates and trends in current and emerging technologies, including experimental failure data and reliability characterization of deployed systems.
New error mitigation techniques, fault-injection tools, robust software frameworks, and error handling protocols for resilient system design.
Case studies analyzing the overhead, effectiveness, and design complexity of error mitigation techniques.
Resilience characterization and strategies for machine learning applications.
Resilience of emerging platforms, cyber-physical and autonomous systems including autonomous vehicles.
Resilience in new architectures, for example accelerator-rich systems and inexact or approximate computing.
The design of resilient systems for space exploration.
The interplay between system security issues and reliability including adversarial attacks/systems.
Program-level error propagation/characterization and visualization of fault tolerance.
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Important Date
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Conference Date
Apr 21
2021
toApr 22
2021
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Jan 19 2021
Draft paper submission deadline
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Mar 08 2021
Draft Paper Acceptance Notification
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Apr 22 2021
Registration deadline
Sponsored By
Contact Information
Previous Conferences
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2022-05-19
2022 18th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE) -
2019-03-26 United States Palo Alto
2019 15th IEEE Workshop on Silicon Errors in Logic - System Effects -
2018-04-03 United States
2018 14th IEEE Workshop on Silicon Errors in Logic - System Effects -
2017-03-21 United States Boston,USA
2017 13th IEEE Workshop on Silicon Errors in Logic - System Effects -
2016-03-29 United States Austin
2016 12th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE) -
2015-03-31 United States
The 11th Workshop on Silicon Errors in Logic - System Effects -
2014-04-01 United States
2014 IEEE Workshop on Silicon Errors in Logic - System Effects -
2013-03-26 United States
2013 IEEE Workshop on Silicon Errors in Logic - System Effects
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