Introduction
The IEEE Microelectronics Design & Test Symposium (MDTS) provides a forum for academic and industry researchers and engineers to discuss the latest advances in microelectronics, share their visions in modern microelectronic technologies, and foster academic-industry collaboration. The 32nd MDTS will feature AI, ML and DL, the impact of which is two-fold. On the one hand, AI/ML algorithms can be used to improve design and test by evaluating the accuracy and effectiveness of models, design rules, and test coverage. On the other hand, new circuits and chip architectures for AI/ML applications are emerging, presenting new challenges to design and test in the form of reticle-size die, chiplets, and hardware/software co-design.
Sponsor Type:2; 3
Committee
Kelly Okunzzi – Marvell Semi
Andy Laidler – ON Semi
Uma Srinivasan – IBM
Eugene Atwood – IBM
Carl Wisnesky – Cadence
Krishna Chakravadhanula – Cadence
Malinky Ghosh – IBM
Charles Thangaraj – Univ. of St. Thomas
Ryan Patterson – CACI
Kevin Gorman – Marvell
Huamin Li – SUNY Buffalo
Xinghao Chen – IEEE
Ted Cooley – Cooley & Company
Themistoklis Haniotakis – S. Illinois Univ.
Yu Zhang – Aptiv
Call for paper
Important date
Submission Topics
· Methods and Procedures for Implementing AI in Design and Test of Microelectronics
· Extending Design and Test Targets and Limits Using AI
· Challenges in generating public domain or academic machine learning datasets (specific to Microelectronics) in use to demonstrate AI, ML and DL for the ETL (Extract, Transform and Load) process
· IOT, edge nodes, or pipelines for real-time data visualizations and monitoring of Microelectronic Design and Test processes and their implications on security
· Applications of Software Engineering to process and analyze Microelectronics Design and Test data
· Barriers to deploying AI/ML/DL technologies and methods to Microelectronics Design, Test, and Research practitioners
· Adopting AI, ML, and DL to manage supply chain and semiconductor test yield challenges
· Circuit design and test requirements and advancements to support AI applications implemented in hardware: new devices, compute-in-memory, high-speed serdes, etc.
· Design and test chip architecture challenges for AI applications
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Important Date
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Conference Date
May 08
2023
toMay 10
2023
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Feb 26 2023
Draft paper submission deadline
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May 10 2023
Registration deadline
Sponsored By
IEEE Schenectady Section
Contact Information
Previous Conferences
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2023-06-12 China Shanghai
The 5th China Manufacturing Digital Transformation Summit 2023 -
2022-05-23 United States Albany
2022 IEEE 31st Microelectronics Design & Test Symposium -
2021-05-18 United States Albany
2021 IEEE Microelectronics Design & Test Symposium
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