Seventh IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits – 3D-Test Workshop

Nov. 15 - 17, 2016

Fort Worth,USA · United States

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Program

Timezone：Asia/Beijing

Program Overview

Important Date

Conference Date

Nov 15

2016

to

Nov 17

2016
Oct 01 2016

Draft paper submission deadline
Nov 01 2016

Final Paper Deadline
Nov 17 2016

Registration deadline

Contact Information

ye******@synopsys.com
165*********

Erik Jan Marinissen
er******@imec.be
32-*********

Shi-Yu Huang
sy******@ee.nthu.edu.tw
886*********

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Previous Conferences

2014-10-23 United States
Fifth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
2013-09-12 United States
Fourth IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits