2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

• Yield Analysis and Modeling

Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics.

• Testing Techniques

Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity.

• Design For Testability in IC Design

FPGA, SoC, NoC, ASIC, low power design and microprocessors.

• Error Detection, Correction, and Recovery

Self-testing and self-checking design; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural-specific techniques; system-level design-time or runtime strategies.

• Dependability Analysis and Validation

Fault injection techniques and frameworks; system's dependability and vulnerability characterization.

• Repair, Restructuring and Reconfiguration

Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems.

• Design for Defect and Fault Tolerance

Reliable circuit/system synthesis; radiation hardened/tolerant processes and design; design space exploration for dependable systems; transient/soft faults and errors.

• Aging and Lifetime Reliability

Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery.

• Dependable Applications and Case Studies

Methodologies and case study applications to Internet of Things, automotive, railway, avionics and space, autonomous systems, industrial control, etc.

• Emerging Technologies

Techniques for 3D stacked ICs, quantum computing architectures, microfluid biochips, etc.

• Design for Security

Fault attacks; fault tolerance-based countermeasures; hw security assurance, hw trojans, resistance to persistent DoS, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability.