2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

The Program Committee cordially invites you to participate and submit your contribution to DFT 2014. The conference topics include, but are not limited to, the following: Yield Analysis and Modeling Defect/Fault analysis and models; statistical yield modeling; critical area and metrics. Testing Techniques Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; signal and clock integrity. Error Detection, Correction, and Recovery Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques. Dependability Analysis and Validation Fault injection techniques and environments; dependability characterization. Defect and Fault Tolerance Reliable circuit/system synthesis; radiation hardened/tolerant processes & design; design space exploration for dependable systems, transient/soft faults and errors. Design For Testability in IC Design FPGA, SoC, NoC, ASIC, microprocessors. Repair, Restructuring and Reconfiguration Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing. Totally Fail-Safe Design for Critical Applications Methodologies and case study applications to automotive, railway, avionics, industrial control, biomedicine, space and smart power networks. Emerging Technologies DFT techniques for CNTs, QCA, DNA, RTDs, SETs, molecular devices and self-assembly. Hardware security Fault attacks, fault tolerance-based counter- measures, Scan-based attacks and countermeasures, hardware trojans, security vs reliability trade-offs, interaction between VLSI test, trust, and reliability.