Introduction
DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest.
Committee
General Chairs
Prashant Joshi Intel, United States prashant.d.joshi@intel.com
Luigi Dilillo LIRMM, France luigi.dilillo@lirmm.fr
Program Chairs
Luca Cassano Politecnico di Milano, Italy luca.cassano@polimi.it
Sreejit Chakravarty Intel sreejit.chakravarty@intel.com
Special Session
Kanad Basu University of Texas, United States kanad.basu@utdallas.edu
Publicity
Pedro Reviriego Universidad Carlos III de Madrid, Spain revirieg@it.uc3m.es
Majed Valad Beigi AMD majed.valadbeigi@amd.com
Industrial Liason
Stephan Eggerglues Siemens, Germany stephan_eggersgluess@mentor.com
Sudhanva Gurumurthi AMD sudhanva.gurumurthi@amd.com
Publication
Alberto Bosio École Central de Lyon, France alberto.bosio@ec-lyon.fr
Audio/Visual
Lucas Matana Luza LIRMM, France lucas.matana-luza@lirmm.fr
Andre Mattos LIRMM, France andre.martins-pio-de-mattos@lirmm.fr
Web
Douglas Santos LIRMM, France douglas.almeida-dos-santos@lirmm.fr
Call for paper
Important date
DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation ar e of interest.
Submission Topics
- Yield Analysis and Modeling
Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics. - Testing Techniques
Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity. - Design For Testability in IC Design
FPGA, SoC, NoC, ASIC, low power design and microprocessors. - Error Detection, Correction, and Recovery
Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural and system-level techniques. - Dependability Analysis and Validation
Fault injection techniques and frameworks; dependability and characterization. - Repair, Restructuring and Reconfiguration
Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems. - Radiation effects
SEEs on nanotechnologies; modeling of radiation environments; radiation experiments; radiation hardening techniques. - Defect and Fault Tolerance
Reliable circuit/system synthesis; fault tolerant processes and design; design space exploration for dependable systems, transient/soft faults. - Aging and Lifetime Reliability
Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery. - Dependable Applications and Case Studies
Methodologies and case studies for IoTs, automotive, railway, avionics and space, autonomous systems, industrial control, etc. - Emerging Technologies
Techniques for 2.5D/3D ICs, quantum computing architecttures, memristors, spintronics, microfluidics, etc. - Design for Security
Fault attacks, fault tolerance-based countermeasures, scan-based attacks and countermeasures, hardware trojans, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability.
All Comments
Important Date
-
Conference Date
Oct 12
2022
toOct 14
2022
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May 07 2022
Draft paper submission deadline
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Jul 08 2022
Draft Paper Acceptance Notification
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Oct 14 2022
Registration deadline
Sponsored By
Contact Information
- Douglas A. dos Santos
- da******@lirmm.fr
Previous Conferences
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2024-10-08 United Kingdom Didcot
2024 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) -
2022-10-08 Macao, China Macao
第25届IEEE智能交通系统国际会议 -
2021-10-19
2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems -
2018-10-08 United States
2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems -
2017-10-23 United Kingdom
2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems -
2016-09-19 United States CT, USA
2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems -
2014-10-01 Netherlands
2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems -
2013-10-02 United States
2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
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