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Introduction

The IEEE European Test Symposium (ETS) is Europe’s premier forum dedicated to presenting and discussing scientific results, emerging ideas, applications, hot topics, and new trends in the area of electronic-based circuit and system testing and reliability. In 2018, ETS will take place at Swissôtel, Bremen, Germany. It is organized by the University of Bremen, which co-sponsors the event jointly with the IEEE Council on Electronic Design Automation (CEDA). ETS traditionally enjoys a strong balance among academic and industrial participants. In addition to regular Scientific Papers, Special Sessions, Panels, and Embedded Tutorials, ETS features Vendor Sessions and Table-Top Demos as well as a special track on Emerging Test Strategies (ETS2) where new issues are presented by the industry and are discussed in an informal atmosphere. ETS is the major event of the European Test Week, which includes TSS (Test Spring School) and fringe workshops.

Call for paper

Important date

2017-12-04
Draft paper submission deadline
2018-02-13
Draft paper acceptance notification
2018-03-18
Final paper submission deadline

Submission Topics

In summary, areas of interest include (but are not limited to):

  • Analog Test

  • ATE Hardware and Software

  • Automatic Test Generation

  • Board Test and Diagnosis

  • Boundary Scan Test

  • Built-In Self-Test (BIST)

  • Current-Based Test

  • Defect-Based Test

  • Delay and Performance Test

  • Dependability and Functional Safety

  • Design for Test (DfT)

  • Design for Manufacturing (DfM)

  • Diagnosis and Silicon Debug

  • Economics of Test

  • Test of Emerging Technologies

  • Failure Analysis

  • Fault Modeling and Simulation

  • Fault Tolerance

  • GPU Test

  • High-Speed I/O Test

  • Low-Power IC Test

  • Memory Test and Repair

  • MEMS Test

  • Microprocessor Test

  • Mixed-Signal Test

  • Multi-/Many-core Processor Test

  • Nanotechnology Test

  • On-line Test

  • Power Issues in Test

  • Reconfigurable System Test

  • Reliability

  • RF Test

  • Security and Trust Issues in Test

  • Self-Repair

  • Sensor Test

  • Signal Integrity Test

  • SiP, Stacked, 3D IC Test

  • SoC Test

  • Soft Errors

  • Standards in Test

  • Statistical Learning in Test

  • Test Compression

  • Test Quality

  • Test Synthesis

  • Thermal Issues in Test

  • Validation and Verification

  • Variability Issues in Test

  • Yield Analysis and Enhancement

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Important Date
  • Conference Date

    May 28

    2018

    to

    Jun 01

    2018

  • Dec 04 2017

    Draft paper submission deadline

  • Feb 13 2018

    Draft Paper Acceptance Notification

  • Mar 18 2018

    Final Paper Deadline

  • Jun 01 2018

    Registration deadline

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