2 / 2023-06-19 21:58:29
A Compact and Robust 28nm CMOS Temperature Sensor with Machine Learning Assisted Design for DVFS SoC
CMOS temperature sensor,subthreshold,Multitasking Evolutionary,DVFS
Draft Pending
Yizhi Ding / Southeast University
Haochang Zhi / Southeast University
Jintao Li / Shenzhen Institute for Advanced Study, University of Electronic Science and Technology of China
Zhuo Chen / Southeast University
Kaiyue Yang / Southeast University
Weiwei Shan / Southeast University
We propose a MOS-based temperature sensor that converts temperature to proportional to absolute temperature (PTAT) current and reference (REF) current using the temperature dependence of subthreshold transistors. Incorporating a self-referenced sensor eliminates the need to manage complex clock trees within DVFS systems. The sensor is designed to operate under a local digital supply which reduces the number of power domains required. For that purpose, the proposed sensor matches the output of two symmetry closed-loop current generator and the ring oscillators (RO) at 25°C, that reduce power sensitivity but sacrifice linearity. We maximize these performance trade-offs with a machine learning (ML) assisted design method, which automatically identifies transistor sizes with minimal PVT deviation, maps the design space, and establishes performance correlations. Moreover, using closed-loop current generation and indirect Miller compensation that enhances the gain-bandwidth resulting the proposed sensor can be powered by a noisy digital supply.

The sensor is implemented and measured in 28nm CMOS and occupies an area of 0.0075mm2 while consuming 18.14μW. Systematical nonlinearity results in a relative inaccuracy of 3.1% after two-point trim. The sensor achieves a 0.25K resolution in a 2.44ms conversion time. The measured supply sensitivity is 7.4°C/V from 0.8V to 1.05V. 

Operating under a local digital supply, the proposed sensor provides the widest supply voltage range, lowest supply sensitivity and is competitive in area, resolution, and conversion time. Moderate accuracy is achieved after compromise of the above performance. Figure 7 depicts a die photograph of the packaged SoC, coupled with the sensor layout, the position of the sensor in the SoC, and its testing setup. As far as monitoring temperature is concerned, the proposed sensor can perfectly accommodate the needs of the DVFS SoC.
Important Date
  • Conference Date

    Nov 05

    2023

    to

    Nov 08

    2023

  • Nov 08 2023

    Registration deadline

Sponsored By
IEEE Solid-State Circuits Society