Introduction

Over the past sixteen years, this workshop has evolved into a forum of exchange on the latest research and developments on innovative schemes for signal and power integrity, and in the field of interconnect modeling, simulation and measurement at chip board and package levels. The workshop is also meant to bring together developers and researchers from industry and academia in order to encourage cooperation. In view of last year's success, the Committee is looking forward to the 17th Edition which will convene at the Hotel Concorde La Fayette in Paris, France.

Call for paper

Submission Topics

TOPICS Emerging and advanced issues, New design techniques and innovative architectures Novel CAD concepts, methodologies and algorithms for modeling, simulation and optimization, with emphasis on: Innovative schemes for SI and PI Noise reduction techniqu
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Important Date
  • Conference Date

    May 12

    2013

    to

    May 15

    2013

  • May 15 2013

    Registration deadline

Sponsored By
IEEE Components
Packaging and Manufacturing Technology Society
Contact Information